Class g audio amplifiers and associated methods of operation

ABSTRACT

The present technology is directed to class G audio amplifiers and the associated methods of operation. In one embodiment, a class G audio amplifier includes an input port, an audio output stage, a level detector, and a charge pump. The class G audio amplifier regulates the power supplies of the audio output stage according to the input signal, so as to realize high efficiency and high quality audio output.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority to Chinese Patent ApplicationNo. 200910308523.1, filed Oct. 20, 2009, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present application relates generally to class G audio amplifiercircuits and associated methods of operation.

BACKGROUND

Class AB amplifiers typically have good output, but low efficiencies. Inorder to improve efficiency and maintain good output, class G amplifierwas introduced. The operation principle of class G amplifiers is similarto class AB amplifiers. In contrast to class AB amplifiers, the powersupply of class G amplifiers is variable as the input signal varies, sothat a voltage across the audio output stage is low to increase theefficiency.

FIG. 1 illustrates a prior art single-supply class AB amplifier 10. Asshown in FIG. 1, the single-supply class AB amplifier 10 comprises audiooutput stages 11 and 12, both of which are powered by a positive powersupply (V_(DD)); speakers 13, 14, and blocking capacitors 15, 16. Theblocking capacitors 15, 16 are used to block a DC bias. Typically, theDC bias is about 0.5V_(DD). So the capacitance of the blockingcapacitors 15, 16 are large, e.g. 470 μF. The high capacitance of mayinterfere with external circuit, enlarge the size of the amplifier, andincrease costs of manufacturing.

FIG. 2 illustrates a prior art amplifier circuit 20 that adopts a chargepump to power audio output stages. In contrast to the single-supplyclass AB amplifier 10 shown in FIG. 1, the amplifier circuit 20comprises a charge pump that provides a negative power supply (V_(SS))to power output stages 11, 12. The negative power supply (V_(SS)) hasthe same amplitude as the positive power supply (V_(DD)), but with adifferent polarity. As a result, the amplifier circuit 20 does notrequire a high capacitance blocking capacitor. Instead, the amplifiercircuit 20 includes a capacitor 21 and a fly capacitor 22 with lowcapacitance, e.g. 1 μF. However, when the input signal is small, theloss of the amplifier circuit 20 is high, causing low efficiencies.

FIG. 3 illustrates a prior art amplifier circuit 30 that uses two powersupplies. As shown in FIG. 3, a positive power supply (HPV_(DD)) isprovided by a buck converter including a high-side switch 38, a low-sideswitch 39, an inductor 40, and an output capacitor 41. The duty cyclesof the high-side switch 38 and the low-side switch 39 are regulated asthe input signal varies through a level detector 31, an optimizer 32, anerror amplifier 33, a compensation network 34, a saw-tooth wavegenerator 35, a PWM (pulse width modulation) comparator 36, and adriving circuit 37, so that the positive power supply (HPV_(DD)) isregulated.

A charge pump 43 receives the positive power supply (HPV_(DD)), andprovides a negative power supply (HPV_(SS)) which has the same amplitudeto the positive power supply (HPV_(DD)). The positive power supply(HPV_(DD)) and the negative power supply (HPV_(SS)) are used to power anaudio output stage 42 of the amplifier circuit 30. Both power suppliesof the audio output stage 42 vary as the input signal varies, reducingloss and increasing efficiency. However, the buck converter requires alarge layout, even larger than a Class AB amplifier with a charge pump.The buck converter also has low efficiencies under light load. Thus, anadditional inductor 40 is needed, which can increase costs and generateEMI (Electro Magnetic Interference). Accordingly, there is a need forimproved class G audio amplifiers with high efficiency, small size, andlow cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic circuit of a single-supply class AB audioamplifier in accordance with the prior art.

FIG. 2 illustrates a schematic circuit of an amplifier circuit with acharge pump to power audio output stages in accordance with the priorart.

FIG. 3 illustrates a schematic circuit of an amplifier circuit with twopower supplies in accordance with the prior art.

FIG. 4 illustrates a schematic circuit of a class G audio amplifier inaccordance with embodiments of the technology.

FIG. 5 illustrates a schematic circuit of a class G audio amplifier inaccordance with embodiments of the technology.

FIG. 6A illustrates a schematic work mode of the class G audio amplifierin FIG. 4.

FIG. 6B illustrates another schematic work mode of the class G audioamplifier in FIG. 4.

FIG. 7 illustrates a schematic circuit of a charge pump used in a classG audio amplifier in accordance with embodiments of the technology.

FIG. 8 illustrates switch control signals when the charge pump in FIG. 7operates under ±0.5× mode.

FIG. 9 illustrates switch control signals when the charge pump in FIG. 7operates under ±1× mode.

FIG. 10 illustrates a schematic circuit of a charge pump used in a classG audio amplifier in accordance with embodiments of the technology.

FIG. 11 illustrates switch control signals when the charge pump in FIG.10 operates under ±0.5× mode.

FIG. 12 illustrates switch control signals when the charge pump in FIG.10 operates under ±1× mode.

FIG. 13 illustrates a schematic output signal waveform of the class Gaudio amplifier in accordance with embodiments of the technology.

FIG. 14 illustrates a charge pump suitable for providing output signalsshown in FIG. 13 in accordance with embodiments of the technology.

FIG. 15 illustrates switch control signals when the charge pump in FIG.14 operates under ±⅓× mode.

FIG. 16 illustrates switch control signals when the charge pump in FIG.14 operates under ±½× mode.

FIG. 17 illustrates switch control signals when the charge pump in FIG.14 operates under ±⅔× mode.

FIG. 18 illustrates switch control signals when the charge pump in FIG.14 operates under ±1× mode.

DETAILED DESCRIPTION

Embodiments of class G audio amplifiers and associated methods ofoperation are described in detail herein. In the following description,some specific details, such as example circuits components, are includedto provide a thorough understanding of embodiments of the technology.One skilled in relevant art will recognize, however, that the technologycan be practiced without one or more specific details, or with othermethods, components, materials, etc.

In one embodiment, a class G audio amplifier includes an input port forreceiving an input signal; an audio output stage coupled to the inputport for providing an amplified audio signal; a level detector coupledto the input port for detecting the input signal, and providing a leveldetected signal based on the detecting; a charge pump coupled to thelevel detector for providing a positive power supply and a negativepower supply in response to the level detected signal. The positivepower supply and the negative power supply are used to power the audiooutput stage.

In another embodiment, a method for operating a class G audio amplifierincludes detecting an input signal to get a level detected signal;providing a positive power supply and a negative power supply inresponse to the level detected signal; and providing an amplified audiosignal in response to the input signal, the positive power supply, andthe negative power supply.

FIG. 4 illustrates a schematic circuit of a class G audio amplifier 100in accordance with embodiments of the technology. As shown in FIG. 4,the class G audio amplifier 100 includes an input port for receiving aninput signal (INL); an audio output stage 103 coupled to the input portto receive the input signal (INL) and configured to provide an amplifiedaudio signal (OUTL) to a speaker 107. A level detector 101 is coupled tothe input port for detecting the input signal (INL), and provides alevel detected signal (IN_(DET)) based thereupon.

A charge pump 102 is coupled to the output of the level detector 101 forreceiving the level detected signal (IN_(DET)), and provides a positivepower supply (HPV_(DD)) and a negative power supply (HPV_(SS)) basedthereupon. In one embodiment, the positive power supply (HPV_(DD)) andthe negative power supply (HPV_(SS)) provided by the charge pump 102 arewith the same amplitudes but opposite polarities from each other. Bothpositive power supply (HPV_(DD)) and the negative power supply(HPV_(SS)) are used to power the audio output stage 103. In otherembodiments, the positive power supply (HPV_(DD)) and the negative powersupply (HPV_(SS)) may have different amplitudes.

In one embodiment, the class G audio amplifier 100 further comprises apositive power capacitor 104 connected between a positive output of thecharge pump 102 and ground. A negative power capacitor 105 is connectedbetween a negative output of the charge pump 102 and ground. A flycapacitor 106 is coupled to the charge pump 102. Thus, the positivepower capacitor 104, the negative power capacitor 105, and the flycapacitor 106 are formed independent of the charge pump 102. In otherembodiments, the positive power capacitor 104, the negative powercapacitor 105, and the fly capacitor 106 may be integrated into thecharge pump 102, as shown in the class G audio amplifier 100′ of FIG. 5.The operation principles of class G audio amplifiers 100 and 100′ aregenerally similar. Thus, the following description is based on the classG audio amplifier 100 in FIG. 4 for brevity, though it equally appliedto the class G audio amplifier 100′ of FIG. 5.

In operation, the level detector 101 detects the magnitude of the inputsignal (INL) and provides a level detected signal to the charge pump102. The charge pump 102 receives the level detected signal and providesthe positive power supply (HPV_(DD)) and the negative power supply(HPV_(SS)) based thereupon, so that the power supplies of the audiooutput stage 103 varies according to the variation of the input signal(INL).

FIG. 6A illustrates a schematic work mode of the class G audio amplifier100 in FIG. 4. In one embodiment, the class G audio amplifier 100regulates the amplified audio signal according to the instantaneousvalue of the input signal (INL). When the instantaneous value of theinput signal (INL) is lower than a first preset value (V₁), the chargepump 102 operates at ±0.5× mode, i.e., HPV_(DD)=0.5V_(DD),HPV_(SS)=−0.5V_(DD). As a result, the voltage across the audio outputstage 103 decreases. When the instantaneous value of the input signal(INL) is higher than the first preset value (V₁), the charge pump 102operates at ±1× mode, i.e., HPV_(DD)=V_(DD), HPV_(SS)=−V_(DD). As aresult, the audio output stage 103 provides the amplified audio signalwith essentially no distortion.

FIG. 6B illustrates another schematic work mode of the class G audioamplifier 100 in FIG. 4. In one embodiment, the class G audio amplifier100 regulates the amplified audio signal according to the amplitude ofthe input signal (INL). When the amplitude of the input signal (INL) islower than the first preset value (V₁), the charge pump 102 operates at±0.5× mode, i.e., HPV_(DD)=0.5V_(DD), HPV_(SS)=−0.5V_(DD). As a result,the voltage across the audio output stage 103 decreases. When theamplitude of the input signal (INL) is higher than the first presetvalue (V₁), the charge pump 102 operates at ±1× mode, i.e.,HPV_(DD)=V_(DD), HPV_(SS)=−V_(DD). As a result, the audio output stage103 provides the amplified audio signal with essentially no distortion.

In certain embodiments, during a transition from ±1× mode to ±0.5× mode,if HPV_(DD)>0.5V_(DD), HPV_(SS)>−0.5V_(DD), the charge pump 102 may beidle and is set into a sleep mode. In other embodiments, the charge pump102 may be have other suitable operations.

FIG. 7 illustrates a schematic circuit of a charge pump 202 suitable fora class G audio amplifier in accordance with additional embodiments ofthe technology. As shown in FIG. 7, the charge pump 202 comprises 7switches (identified individually as switches S₁˜S₇), a fly capacitor(C₁), a negative power capacitor (C₂), a positive power capacitor (C₃),a power supply (V_(DD)), and nodes 1˜5. In one embodiment, the positivepower capacitor (C₃) is connected between a positive output of thecharge pump 202 and ground. The negative power capacitor (C₂) isconnected between a negative output of the charge pump 102 and ground.The first terminal of the fly capacitor is coupled to the power supply(V_(DD)), and the second terminal of the fly capacitor is controllablycoupled to the positive output or the negative output of the charge pump202. In one embodiment, switches (S₁˜S₇) may be MOSFETs. However, inother embodiments, the switches may be IGBT, JFET, and/or other suitablecontrollable switch devices.

In one embodiment, the first switch (S₁) is coupled between node 3 andnode 4; the second switch (S₂) is coupled between node 3 and ground; thethird switch (S₃) is coupled between node 1 and node 4; the fourthswitch (S₄) is coupled between node 1 and node 3; the fifth switch (S₅)is coupled between node 1 and node 5; the sixth switch (S₆) is coupledbetween node 5 and ground; the seventh switch (S₇) is coupled betweennode 2 and node 5; the fly capacitor (C₁) is coupled between node 3 andnode 5; the negative power capacitor (C₂) is coupled between node 2 andground; the positive power capacitor (C₃) is coupled between node 1 andground; the power supply (V_(DD)) is coupled between node 4 and ground.In certain embodiments, node 1 is the positive output of the charge pump202, node 2 is the negative output of the charge pump 202. In otherembodiments, different power supplies may be provided when differentcontrol schemes are adopted.

FIG. 8 illustrates switch control signals when the charge pump 202 inFIG. 7 operates under ±0.5× mode. As shown in FIG. 8, the controlsignals of the first switch (S₁) to the seventh switch (S₇) are asfollows: Operation 1, turn on the first switch (S₁) and the fifth switch(S₅), and turn off the rest of the switches. The power supply (V_(DD)),the first switch (S₁), the fly capacitor (C₁), the fifth switch (S₅),and the positive power capacitor (C₃) form a current loop. The voltageacross the fly capacitor (C₁) is charged to be V_(C1), the voltageacross the positive power capacitor (C₃) is charged to be V_(C3),wherein V_(C1)+V_(C3)=V_(DD). And the voltage across the positive powercapacitor (C₃) is positive, i.e., HPV_(DD)=+V_(C3).

Operation 2, turn on the second switch (S₂) and the seventh switch (S₇),and turn off the rest of the switches. The second switch (S₂), the flycapacitor (C₁), the seventh switch (S₇), and the negative powercapacitor (C₂) form a current loop. The fly capacitor (C₁) and thenegative power capacitor (C₂) are coupled in parallel. The fly capacitor(C₁) is discharged by the negative capacitor (C₂). Accordingly, thevoltage across the negative power capacitor (C₂) is V_(C2)=V_(C1). Thevoltage across the negative capacitor (C₂) is negative, i.e.,HPV_(SS)=−V_(C1).

Operation 3, turn on the fourth switch (S₄) and the sixth switch (S₆),and turn off the rest of the switches. The sixth switch (S₆), the flycapacitor (C₁), the fourth switch (S₄), and the positive power capacitor(C₃) form a current loop. The fly capacitor (C₁) and the positive powercapacitor (C₃) are coupled in parallel. Accordingly, the voltage acrossthe fly capacitor (C₁) is equal to the voltage across the positive powercapacitor (C₃), i.e., V_(C1)=V_(C3). As illustrated above,V_(C1)+V_(C3)=V_(DD), so V_(C1)=V_(C3)=0.5V_(DD),HPV_(DD)=V_(C3)=+0.5V_(DD), HPV_(SS)=−V_(C1)=−0.5V_(DD). The processrepeats by executing above three operation to provide stableHPV_(DD)=+0.5V_(DD), HPV_(SS)=−0.5V_(DD), realizing the ±0.5× mode.

FIG. 9 illustrates switch control signals when the charge pump 202 inFIG. 7 operates under ±1× mode. As shown in FIG. 9, the control signalsof the first switch (S₁) to the seventh switch (S₇) are as follows:Operation 1, turn on the first switch (S₁), the third switch (S₃) andthe sixth switch (S₆), and turn off the rest of the switches. The powersupply (V_(DD)), the first switch (S₁), the fly capacitor (C₁), and thesixth switch (S₆) form a current loop. Meanwhile, the power supply(V_(DD)), the third switch (S₃), and the positive power capacitor (C₃)also form a current loop. The voltage across the fly capacitor (C₁) andthe voltage across the positive capacitor (C₃) are charged to be V_(DD).And both voltages are positive, i.e., HPV_(DD)=+V_(DD).

Operation 2, turn on the second switch (S₂) and the seventh switch (S₇),maintain the third switch (S₃) on, and turn off the rest of theswitches. The second switch (S₂), the fly capacitor (C₁), the seventhswitch (S₇), and the negative power capacitor (C₂) form a current loop.The fly capacitor (C₁) and the negative power capacitor (C₂) are coupledin parallel. The fly capacitor (C₁) is discharged by the negativecapacitor (C₂). Accordingly, the voltage across the negative powercapacitor (C₂) is V_(C2)=V_(DD). And the voltage across the negativecapacitor (C₂) is negative, i.e., HPV_(SS)=−V_(DD). The process repeatsby executing above two operations to provide stable HPV_(DD)=+V_(DD),HPV_(SS)=−V_(Co), realizing the ±1× mode.

FIG. 10 illustrates a schematic circuit of a charge pump 302 suitablefor a class G audio amplifier in accordance with additional embodimentsof the technology. In contrast to the charge pump 202 in FIG. 7, thecharge pump 302 includes a first diode (D₅) in place of the fifth switch(S₅), and a second diode (D₇) in place of the seventh switch (S₇). Therest of the charge pump 302 is generally similar to the charge pump 202.

FIG. 11 illustrates switch control signals when the charge pump 302 inFIG. 10 operates under ±0.5× mode. As shown in FIG. 11, the controlsignals of the first switch (S₁) to the sixth switch (S₆) are asfollows: Operation 1, turn on the first switch (S₁), and turn off therest of the switches. The power supply (V_(DD)), the first switch (S₁),the fly capacitor (C₁), the first diode (D₅), and the positive powercapacitor (C₃) form a current loop. The voltage across the fly capacitor(C₁) is charged to be V_(C1), the voltage across the positive powercapacitor (C₃) is charged to be V_(C3), wherein V_(C1)+V_(C3)=V_(DD).And both voltage are positive, i.e., HPV_(DD)=V_(C3).

Operation 2, turn on the second switch (S₂), and turn off the rest ofthe switches. The second switch (S₂), the fly capacitor (C₁), the seconddiode (D₇), and the negative power capacitor (C₂) form a current loop.The fly capacitor (C₁) and the negative power capacitor (C₂) are coupledin parallel. The fly capacitor (C₁) is discharged by the negativecapacitor (C₂). Accordingly, the voltage across the negative powercapacitor (C₂) is V_(C2)=V_(C1). And the voltage across the negativecapacitor (C₂) is negative, i.e., HPV_(SS)=−V_(C1).

Operation 3, turn on the fourth switch (S₄) and the sixth switch (S₆),and turn off the rest of the switches. The sixth switch (S₆), the flycapacitor (C₁), the fourth switch (S₄), and the positive power capacitor(C₃) form a current loop. The fly capacitor (C₁) and the positive powercapacitor (C₃) are coupled in parallel. Accordingly, the voltage acrossthe fly capacitor (C₁) is equal to the voltage across the positive powercapacitor (C₃), i.e., V_(C1)=V_(C3). As illustrated above,V_(C1)+V_(C3)=V_(DD), so V_(C1)=V_(C3)=+0.5V_(DD),HPV_(DD)=V_(C3)=+0.5V_(DD), HPV_(SS)=−V_(C1)=−0.5V_(DD). The processrepeats by executing above three operation to provide stableHPV_(DD)=+0.5V_(DD), HPV_(SS)=−0.5V_(DD), realizing the ±0.5× mode.

FIG. 12 illustrates switch control signals when the charge pump 302 inFIG. 10 operates under ±1× mode. As shown in FIG. 12, the controlsignals of the first switch (S₁) to the sixth switch (S₆) are asfollows: Operation 1, turn on the first switch (S₁), the third switch(S₃) and the sixth switch (S₆), and turn off the rest of the switches.The power supply (V_(DD)), the first switch (S₁), the fly capacitor(C₁), and the sixth switch (S₆) form a current loop. Meanwhile, thepower supply (V_(DD)), the third switch (S₃), and the positive powercapacitor (C₃) also form a current loop. The voltage across the flycapacitor (C₁) and the voltage across the positive capacitor (C₃) areboth charged to be V_(DD). And both voltages are positive, i.e.,HPV_(DD)=+V_(DD).

Operation 2, turn on the second switch (S₂), and keep the third switch(S₃) on, and turn off the rest of the switches. The second switch (S₂),the fly capacitor (C₁), the second diode (D₇), and the negative powercapacitor (C₂) form a current loop. The fly capacitor (C₁) and thenegative power capacitor (C₂) are coupled in parallel. The fly capacitor(C₁) is discharged by the negative capacitor (C₂). Accordingly, thevoltage across the negative power capacitor (C₂) is V_(C2)=V_(DD). Andthe voltage across the negative capacitor (C₂) is negative, i.e.,HPV_(SS)=−V_(DD). The process repeats by executing the two foregoingoperations to provide stable HPV_(DD)=+V_(DD), HPV_(SS)=−V_(DD),realizing the ±1× mode.

As illustrated hereinbefore, the first switch (S₁) and the third switch(S₃) are operated in ON/OFF mode. However, that in other embodiment, thefirst switch (S₁) and the third switch (S₃) may operate as acontrollable current source. For example, when the first switch (S₁) isturned on, the power supply (V_(DD)) and the first switch (S₁) areequivalent to a controllable current source, so that the voltage acrossthe fly capacitor (C₁) increases slowly. When the first switch (S₁) isturned off, the power supply (V_(DD)) and the fly capacitor (C₁) aredisconnected. Similarly, when the third switch (S₃) is turned on, thepower supply (V_(DD)) and the third switch (S₃) are equivalent to acontrollable current source, so that the voltage across the positivepower capacitor (C₃) increases slowly. When the third switch (S₃) isturned off, the power supply (V_(DD)) and the positive power capacitor(C₃) are disconnected.

Furthermore, the class G audio amplifier in accordance with yet furtherembodiments of the technology may provide more than 2-level powersupplies. For example, the class G audio amplifier may provide N-levelpower supplies, e.g., ±V_(DD)/N, ±2*V_(DD)/N, ±3*V_(DD)/N, . . . ,±(N−2)*V_(DD)/N, ±(N−1)*V_(DD)/N, ±V_(DD), where N is a natural number.When N-level power supplies are used, the fly capacitor (C₁) is replacedby (N−1) capacitors coupled in series.

FIG. 13 illustrates a schematic output signal waveform of the class Gaudio amplifier 100 with N=3. In one embodiment, when the instantaneousvalue of the input signal (INL) is lower than a second preset value(V₂), the charge pump 102 operates at ±⅓× mode, i.e., HPV_(DD)=⅓V_(DD),HPV_(SS)=−⅓V_(DD). When the instantaneous value of the input signal(INL) is lower than the second preset value (V₂) but higher than a thirdpreset value (V₃), the charge pump 102 operates at ±½× mode, i.e.,HPV_(DD)=½V_(DD), HPV_(SS)=−½V_(DD). When the instantaneous value of theinput signal (INL) is higher than the third preset value (V₂) but lowerthan a fourth preset value (V₄), the charge pump 102 operates at ±⅔×mode, i.e., HPV_(DD)=⅔V_(DD), HPV_(SS)=−⅔V_(DD). When the instantaneousvalue of the input signal (INL) is higher than the fourth preset value(V₄), the charge pump 102 operates at ±1× mode, i.e., HPV_(DD)=V_(DD),HPV_(SS)=−V_(DD).

In one embodiment, during a transition from a high mode to a low mode,e.g., from ±1× mode to ±0.5× mode, if the output of the charge pump 102is higher than a desired output, the charge pump 102 may be idle and isset into a sleep mode. In other embodiments, the charge pump 102 mayhave other suitable operations.

In certain embodiments, the charge pump 102 transforms from one mode toanother mode in response to the instantaneous value of the input signal.However, in other embodiments, the charge pump 102 may transform fromone mode to another mode in response to the amplitude of the inputvalue.

FIG. 14 illustrates a charge pump 402 suitable for realizing outputsignals shown in FIG. 13 in accordance with further embodiments of thetechnology. In one embodiment, N=3, and the single fly capacitor (C₁) isreplaced by two capacitors, i.e., a first fly capacitor (C₁) and asecond capacitor (C₄). The charge pump 402 comprises switches (S₁˜S₁₀),the first fly capacitor (C₁), a negative power capacitor (C₂), apositive power capacitor (C₃), the second fly capacitor (C₄), an powersupply (V_(DD)), and nodes 1˜7.

In contrast to the charge pump 202 in FIG. 7, there are two more nodes 6and 7 between node 3 and node 5. The first fly capacitor (C₁) is coupledbetween node 3 and node 6; the second fly capacitor (C₄) is coupledbetween node 5 and node 7; an eighth switch (S₅) is coupled between node3 and node 7; a ninth switch (S₉) is coupled between node 5 and node 6;a tenth switch (S₁₀) is coupled between node 6 and node 7. The rest ofthe charge pump 402 is generally similar to that of the charge pump 202.Different power supplies could be provided at node 1 and node 2 whendifferent control schemes are adopted.

FIG. 15 illustrates switch control signals when the charge pump 402 inFIG. 14 operates under ±⅓× mode. As shown in FIG. 15, the controlsignals of the first switch (S₁) to the tenth switch (S₁₀) are asfollows: Operation 1, turn on the first switch (S₁), the fifth switch(S₅) and the tenth switch (S₁₀), and turn off the rest of the switches.The power supply (V_(DD)), the first switch (S₁), the first flycapacitor (C₁), the tenth switch (S₁₀), the second fly capacitor (C₄),the fifth switch (S₅), and the positive power capacitor (C₃) form acurrent loop. The voltage across the first fly capacitor (C₁) is chargedto be V_(C1), the voltage across the positive power capacitor (C₃) ischarged to be V_(C3), the voltage across the second fly capacitor (C₄)is charged to be V_(C4), and V_(C1)+V_(C3)+V_(C4)=V_(DD). The voltageacross the positive capacitor (C₃) is positive, i.e., HPV_(DD)=V_(C3).

Operation 2, turn on the second switch (S₂), the seventh switch (S₇),the eighth switch (S₈) and the ninth switch (S₉), and turn off the restof the switches. The second switch (S₂), the eighth switch (S₈), thesecond fly capacitor (C₄), the seventh switch (S₇), and the negativepower capacitor (C₂) form a current loop. Meanwhile, the second switch(S₂), the first fly capacitor (C₁), the ninth switch (S₉), the seventhswitch (S₇), and the negative power capacitor (C₂) also form a currentloop. The first fly capacitor (C₁), the second fly capacitor (C₄) andthe negative power capacitor (C₂) are coupled in parallel. The first flycapacitor (C₁) and the second fly capacitor (C₄) are discharged by thenegative capacitor (C₂). Accordingly, the voltage across the negativepower capacitor (C₂) is V_(C2)=V_(C1)=V_(C4). And the voltage across thenegative capacitor (C₂) is negative, i.e., HPV_(SS)=−V_(C1).

Operation 3, turn on the fourth switch (S₄), the sixth switch (S₆), theeighth switch (S₈) and the ninth switch (S₉), and turn off the rest ofthe switches. The sixth switch (S₆), the ninth switch (S₉), the firstfly capacitor (C₁), the fourth switch (S₄), and the positive powercapacitor (C₃) form a current loop. Meanwhile, the sixth switch (S₆),the second fly capacitor (C₄), the eighth switch (S₈), the fourth switch(S₄), and the positive power capacitor (C₃) also form a current loop.The first fly capacitor (C₁), the second fly capacitor (C₄), and thepositive power capacitor (C₃) are coupled in parallel. Accordingly, thevoltage across the positive power capacitor (C₃) isV_(C3)=V_(C1)=V_(C4). As illustrated above, V_(C1)+V_(C3)+V_(C4)=V_(DD).Thus, V_(C1)=V_(C3)=V_(C4)=½V_(DD), HPV_(DD)=V_(C3)=+⅓V_(DD),HPV_(SS)=−V_(C1)=−⅓V_(DD). The process repeats by executing the threeOperations above to provide stable HPV_(DD)=+⅓V_(DD), HPV_(SS)=−⅓V_(DD),realizing the ±⅓× mode.

FIG. 16 illustrates switch control signals when the charge pump 402 inFIG. 14 operates under ±0.5× mode. As shown in FIG. 16, the controlsignals of the first switch (S₁) to the tenth switch (S₁₀) are asfollows: Operation 1, turn on the first switch (S₁), the fifth switch(S₅), the eighth switch (S₈) and the ninth switch (S₉), and turn off therest of the switches. The power supply (V_(DD)), the first switch (S₁),the first fly capacitor (C₁), the ninth switch (S₉), the fifth switch(S₅); and the positive power capacitor (C₃) form a current loop.Meanwhile, the power supply (V_(DD)), the first switch (S₁), the eighthswitch (S₅), the second fly capacitor (C₄), the fifth switch (S₅), andthe positive power capacitor (C₃) also form a current loop. The firstfly capacitor (C₁) and the second fly capacitor (C₄) are coupled inparallel, which is further coupled with the negative power capacitor(C₂) in series between the power supply (V_(DD)) and ground. The voltageacross the first fly capacitor (C₁) is charged to be V_(C1), the voltageacross the second fly capacitor (C₄) is charged to be V_(C4), and thevoltage across the positive power capacitor (C₃) is charged to beV_(C3), wherein V_(C1)=V_(C4), V_(C1)+V_(C3)=V_(DD). And the voltageacross the positive capacitor (C₃) is positive, i.e., HPV_(DD)=V_(C3).

Operation 2, turn on the second switch (S₂) and the seventh switch (S₇),keep the eighth switch (S₈) and the ninth switch (S₉) ON, and turn offthe rest of the switches. The second switch (S₂), eighth switch (S₅),the second fly capacitor (C₄), the seventh switch (S₇), and the negativepower capacitor (C₂) form a current loop. Meanwhile, the second switch(S₂), the first fly capacitor (C₁), the ninth switch (S₉), the seventhswitch (S₇), and the negative power capacitor (C₂) also form a currentloop. The first fly capacitor (C₁), the second fly capacitor (C₄) andthe negative power capacitor (C₂) are coupled in parallel. The first flycapacitor (C₁) and second fly capacitor (C₄) are discharged by thenegative capacitor (C₂). Accordingly, the voltage across the negativepower capacitor (C₂) is V_(C2)=V_(C1)=V_(C4). And the voltage across thenegative capacitor (C₂) is negative, i.e., HPV_(SS)=−V_(C1).

Operation 3, turn on the fourth switch (S₄) and the sixth switch (S₆),keep the eighth switch (S₈) and the ninth switch (S₉) ON, and turn offthe rest of the switches. The sixth switch (S₆), the ninth switch (S₉),the first fly capacitor (C₁), the fourth switch (S₄), and the positivepower capacitor (C₃) form a current loop. Meanwhile, the sixth switch(S₆), the second fly capacitor (C₄), the eighth switch (S₈), the fourthswitch (S₄), and the positive power capacitor (C₃) also form a currentloop. The first fly capacitor (C₁), the second fly capacitor (C₄) andthe positive power capacitor (C₃) are coupled in parallel. Accordingly,the voltages across the positive power capacitor (C₃) isV_(C3)=V_(C1)=V_(C4). As illustrated above, V_(C1)+V_(C3)=V_(DD), soV_(C1)=V_(C3)=V_(C4)=½V_(DD), HPV_(DD)=V_(C3)=+½V_(DD),HPV_(SS)=−V_(C1)=−½V_(DD). The process repeats by executing the threeOperations above to provide stable HPV_(DD)=+½V_(DD), HPV_(SS)=−½V_(DD),realizing the ±½× mode.

FIG. 17 illustrates switch control signals when the charge pump 402 inFIG. 14 operates under ±⅔× mode. As shown in FIG. 17, the controlsignals of the first switch (S₁) to the tenth switch (S₁₀) are asfollows: Operation 1, turn on the first switch (S₁), the fifth switch(S₅), the eighth switch (S₈) and the ninth switch (S₉), and turn off therest of the switches. The power supply (V_(DD)), the first switch (S₁),the first fly capacitor (C₁), the ninth switch (S₉), the fifth switch(S₅), and the positive power capacitor (C₃) form a current loop.Meanwhile, the power supply (V_(DD)), the first switch (S₁), the eighthswitch (S₉), the second fly capacitor (C₄), the fifth switch (S₅), andthe positive power capacitor (C₃) also form a current loop. The firstfly capacitor (C₁) and the second fly capacitor (C₄) are coupled inparallel, which is further coupled with the positive power capacitor(C₃) in series between the power supply (V_(DD)) and ground. The voltageacross the fly capacitor (C₁) is charged to be V_(C1), the voltageacross the second fly capacitor (C4) is charged to be V_(C4), thevoltage across the positive power capacitor (C₃) is charged to beV_(C3), wherein V_(C1)=V_(C4), V_(C1)+V_(C3)=V_(DD). And the voltageacross the positive capacitor (C₃) is positive, i.e., HPV_(DD)=+V_(C3).

Operation 2, turn on the second switch (S₂), the seventh switch (S₇) andthe tenth switch (S₁₀), and turn off the rest of the switches. Thesecond switch (S₂), the first fly capacitor (C₁), the tenth switch(S₁₀), the second fly capacitor (C₄), the seventh switch (S₇), and thenegative power capacitor (C₂) form a current loop. The first flycapacitor (C₁) and the second fly capacitor (C₄) are coupled in series,which is further coupled with the negative power capacitor (C₂) inparallel. The first fly capacitor (C₁) and the second fly capacitor (C₄)are discharged by the negative capacitor (C₂). Accordingly, the voltageacross the negative power capacitor (C₂) is V_(C2)=V_(C1)+V_(C4). Andthe voltage across the negative capacitor (C₂) is positive, i.e.,HPV_(SS)=−V_(C2).

Operation 3, turn on the fourth switch (S₄), the sixth switch (S₆) andthe tenth switch (S₁₀), and turn off the rest of the switches. The sixthswitch (S₆), second fly capacitor (C₄), the tenth switch (S₁₀), thefirst fly capacitor (C₁), the fourth switch (S₄), and the positive powercapacitor (C₃) form a current loop. The first fly capacitor (C₁) thesecond fly capacitor (C₄) are coupled in series, which is furthercoupled with the positive power capacitor (C₃) in parallel. Accordingly,the voltage across the positive power capacitor (C₃) isV_(C3)=V_(C1)+V_(C4). As illustrated hereinbefore, V_(C1)=V_(C4),V_(C1)+V_(C3)=V_(DD), so V_(C1)=V_(C4)=+⅓V_(DD), V_(C3)=+⅔V_(DD),V_(C2)=+⅔V_(DD), HPV_(DD)=V_(C3)=+⅔V_(DD), HPV_(SS)=−⅔V_(DD). Theprocess repeats by executing the three Operations above to providestable HPV_(DD)=+⅔V_(DD), HPV_(SS)=−⅔V_(DD), realizing the ±⅔× mode.

FIG. 18 illustrates switch control signals when the charge pump 402 inFIG. 14 operates under ±1× mode. As shown in FIG. 18, the controlsignals of the first switch (S₁) to the tenth switch (S₁₀) are asfollows: Operation 1, turn on the first switch (S₁), the sixth switch(S₆), the third switch (S₃), the eighth switch (S₈) and the ninth switch(S₉), and turn off the rest of the switches. As a result, the positivepower capacitor (C₃) is charged by the power supply (V_(DD)), i.e.,HPV_(DD)=+V_(DD). The power supply (V_(DD)), the first switch (S₁), thefirst fly capacitor (C₁), the ninth switch (S₉), and the sixth switch(S₆) form a current loop. Meanwhile, the power supply (V_(DD)), thefirst switch (S₁), the eighth switch (S₈), the second fly capacitor(C₄), and the sixth switch (S₆) also form a current loop. The first flycapacitor (C₁) and the second fly capacitor (C₄) are coupled in parallelbetween the power supply (V_(DD)) and ground. So the voltages across thefly capacitor (C₁) and the second fly capacitor (C₄) are charged to beV_(DD).

Operation 2, turn on the second switch (S₂) and the seventh switch (S₇),keep the third switch (S₃), the eighth switch (S₈), and the ninth switch(S₉) on, and turn off the rest of the switches. The positive powercapacitor (C₃) is continued to be charged by the power supply (V_(DD)).The second switch (S₂), the first fly capacitor (CA the ninth switch(S₉), the seventh switch (S₇), and the negative power capacitor (C₂)form a current loop. Meanwhile, the second switch (S₂), the eighthswitch (S₈), the second fly capacitor (C₄), the seventh switch (S₇), andthe negative power capacitor (C₂) also form a current loop. The firstfly capacitor (C₁), the second fly capacitor (C₄) and the negative powercapacitor (C₂) are coupled in parallel. The first fly capacitor (C₁) andthe second fly capacitor (C₄) are discharged by the negative capacitor(C₂). Accordingly, the voltage across the negative power capacitor (C₂)is V_(C2)=V_(C1)=V_(C4)=−V_(DD). And the voltage across the negativecapacitor (C₂) is negative, i.e., HPV_(SS)=−V_(DD). The process repeatsby executing the two Operations above, so that stable HPV_(DD)=+V_(DD),HPV_(SS)=−V_(DD) are provided, and the ±1× mode is realized.

As illustrated hereinbefore, the first switch (S₁) and the third switch(S₃) are operated in ON/OFF mode. However, in other embodiments, thefirst switch (S₁) and the third switch (S₃) may operate as acontrollable current source. The switch control signals illustratedhereinbefore are in voltage domain. However, in other embodiments theswitch control signals may be illustrated in current domain.

Furthermore, the present technology provides a method for operating aclass G audio amplifier. In one embodiment, the method comprisesdetecting an input signal through a level detector to obtain a detectedlevel signal; providing a positive power supply and a negative powersupply through a charge pump in response to the detected level signal;and providing an amplified audio signal through an audio output stage inresponse to the input signal, the positive power supply, and thenegative power supply.

In one embodiment, the positive power supply and the negative powersupply have the same amplitude but with opposite polarities from eachother. The positive power supply and the negative power supply can be±V_(DD)/N, ±2*V_(DD)/N, ±3*V_(DD)/N, . . . , ±(N−2)*V_(DD)/N,±(N−1)*V_(DD)/N, ±V_(DD), where V_(DD) is the voltage value of a powersupply, N is a natural number. In certain embodiments, the amplitude ofthe input signal is detected to obtain the level detected signal. Inother embodiments, the instantaneous value of the input signal isdetected to obtain the level detected signal.

The charge pump can include a power supply, a positive power capacitor,a negative power capacitor and a fly capacitor. The positive powercapacitor is coupled between a positive output of the charge pump andground; the negative power capacitor is coupled between a negativeoutput of the charge pump and ground; the fly capacitor is controllableto be coupled between the power supply and the negative output of thecharge pump or to coupled between the power supply and the positiveoutput of the charge pump.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thetechnology. Many of the elements of one embodiment may be combined withother embodiments in addition to or in lieu of the elements of the otherembodiments. Accordingly, the technology is not limited except as by theappended claims.

1. A class G audio amplifier, comprising: an input port configured toreceive an input signal; an audio output stage coupled to the inputport, wherein the audio output stage is configured to output anamplified audio signal that is based on the input signal; a leveldetector coupled to the input port, wherein the level detector isconfigured to detect a level of the input signal and to output adetected level signal based on the detected level of the input signal; acharge pump coupled to the level detector, wherein the charge pump isconfigured to provide a positive power supply voltage and a negativepower supply voltage in response to the detected level signal, thepositive power supply and the negative power supply being coupled topower the audio output stage.
 2. The class G audio amplifier of claim 1,further comprising a speaker coupled to an output of the audio outputstage.
 3. The class G audio amplifier of claim 1, wherein the leveldetector detects an instantaneous voltage level of the input signal. 4.The class G audio amplifier of claim 1, wherein the level detectordetects an amplitude of the input signal.
 5. The class G audio amplifierof claim 1, wherein the positive power supply and the negative powersupply have the same amplitude but opposite polarities from each other.6. The class G audio amplifier of claim 1, wherein the charge pump isconfigured to operate at ±1/N, ±2/N, . . . , ±(N−2)/N, ±(N−1)/N, ±½x,±1× mode, where N is a natural number.
 7. The class G audio amplifier ofclaim 6, wherein during a transition from a high mode to a low mode, ifan output of the charge pump is higher than a desired value, the chargepump is in a sleep mode.
 8. The class G audio amplifier of claim 6,wherein when N=2, the charge pump comprises: a power supply coupled to apositive output of the charge pump via a third switch; a positive powercapacitor coupled between the positive output of the charge pump andground; a negative power capacitor coupled between a negative output ofthe charge pump and ground; a fly capacitor having a first terminalcontrollably coupled to the power supply via a first switch, coupled tothe positive output of the charge pump via a fourth switch, and coupledto ground via a second switch, a second terminal controllably coupled tothe positive output of the charge pump via a fifth switch, coupled tothe negative output of the charge pump via a seventh switch, and coupledto ground via a sixth switch.
 9. The class G audio amplifier of claim 8,wherein the first switch and the third switch operate as a controllablecurrent source.
 10. The class G audio amplifier of claim 8, wherein thefifth switch includes a diode.
 11. The class G audio amplifier of claim8, wherein the seventh switch includes diode.
 12. The class G audioamplifier of claim 8, wherein when N=3, the fly capacitor includes afirst fly capacitor and a second fly capacitor, wherein the first flycapacitor and the second fly capacitor are controllably coupled inseries via a tenth switch, and controllably coupled in parallel via aneighth switch and a ninth switch.
 13. A class G audio amplifier,comprising: an input port for receiving an input signal; means forproviding an amplified audio signal in response to the input signal;means for detecting a level of the input signal, and providing adetected level signal based on the detected level of the input signal;means for providing a positive power supply and a negative power supplyin response to the detected level signal, wherein the positive powersupply and the negative power supply are coupled to power the means forproviding the amplified audio signal.
 14. The class G audio amplifier ofclaim 13, wherein the means for detecting the input signal detect aninstantaneous voltage of the input signal.
 15. The class G audioamplifier of claim 13, wherein the means for detecting the input signaldetect an amplitude of the input signal.
 16. The class G audio amplifierof claim 13, wherein the positive power supply and the negative powersupply have the same amplitude but opposite polarities from each other.17. The class G audio amplifier of claim 13, wherein the means forproviding the positive power supply and the negative power supplyoperates at ±1/N, ±2/N, . . . , ±(N−2)/N, ±(N−1)/N, ±½×, ±1× mode, whereN is a natural number.
 18. A method of operating a class G audioamplifier, comprising: detecting a level of an input signal; generatinga detected level signal based on the detected level of the input signal;providing a positive power supply and a negative power supply inresponse to the detected level signal; producing an amplified audiosignal in response to the input signal, the positive power supply, andthe negative power supply.
 19. The method in claim 18, wherein detectingthe level of an input signal comprises detecting an amplitude of theinput signal.
 20. The method in claim 18, wherein detecting the level ofan input signal comprises detecting an instantaneous voltage of theinput signal.
 21. The method in claim 18, wherein the positive powersupply and the negative power supply have the same amplitude butopposite polarities from each other.
 22. The method of claim 21 whereinproviding the positive power supply and the negative power supplyincludes providing a positive power supply and a negative power supplywith a voltage that is ±V_(DD)/N, ±2*V_(DD)/N, ±3*V_(DD)/N, . . . ,±(N−2)*V_(DD)/N, ±(N−1)*V_(DD)/N, ±V_(DD), where V_(DD) is a voltagelevel of a general power supply, and N is a natural number.